The invention relates to the formation of semiconductor devices. More specifically, the invention relates to the formation of semiconductor devices using a dual damascene process.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
In semiconductor-based device (e.g., integrated circuits or flat panel displays) manufacturing, dual damascene structures may be used in conjunction with copper conductor material to reduce the RC delays associated with signal propagation in aluminum-based materials used in previous generation technologies. In dual damascene, instead of etching the conductor material, vias, and trenches may be etched into the dielectric material and filled with copper.
To facilitate discussion, FIG. 1A is a cross-sectional view of a stack 100 on a wafer 110 used in the dual damascene process of the prior art. A contact 104 may be placed in a dielectric layer 108 over a wafer 110. A barrier layer 112, which may be of silicon nitride or silicon carbide, may be placed over the contact 104 to prevent the copper diffusion. A low-k dielectric layer 120 may be placed over the barrier layer 112. An antireflective layer (ARL) 116 may be placed over the low-k dielectric layer 120. A patterned resist layer 132 may be placed over the ARL 116. The ARL 116 may be formed from silicon nitride, SiON, or other material with a high refractive index and high extinction coefficient.
In a via first dual damascene process, the stack 100 may be subjected to an etch, which etches a via 140 down to the barrier layer 112, as shown in FIG. 1B. Remaining photoresist mask material is also stripped. For low-k dielectrics such as organosilicate glass (OSG), when the stripping process uses an oxygen strip, exposed portions of the low-k dielectric may be damaged, as shown by damage regions 194 in FIG. 1B. This damage may increase RC delay and parasitic capacitance. A via plug fill may provide a spin on dielectric via plug material 137 which fills the vias and forms a layer over the low-k dielectric layer 120, as shown in FIG. 1C. As feature size decreases the via plug is more susceptible to form voids 139. These voids contribute to production defects. An example of one way that such voids may increase defects is explained below.
A photoresist trench pattern 145 is formed over the via plug material 137, as shown in FIG. 1C. A trench etch is used to form a trench 147, as shown in FIG. 1D. Some of the damaged areas 194 are etched away during the trench etch. Some of the via plug material 137 remains after the trench etch. In this example, due to the presence of large voids, the trench etched has punched through the via plug material and barrier layer 112, at 147 to expose part of a copper contact 104.
A subsequent trench pattern strip is used to remove the trench pattern and the remaining via plug, as shown in FIG. 1E. An oxygen ashing may be used to accomplish the strip. Oxygen ashing or other stripping processes may cause more damage regions 194 in the low-k dielectric and corrosion/oxidation 195 in the exposed portion of the copper contact 104, as shown in FIG. 1E. As a result, this example of a via first dual damascene process may provide damaged low-k dielectric regions and corroded/oxidized contacts.